1. Field of the Invention
This invention relates to a multiprocessor system connecting by a common bus a plurality of processors (CPU; Central Processing Unit) for implementing processings of input/output (I/O) and programs and, more particularly, to a setting-up technique for a symmetric multiprocessor system capable of implementing processings of I/Os and programs at an arbitrary processor.
2. Description of the Related Art
FIG. 16 is a block diagram showing a conventional information processing apparatus, as a symmetric multiprocessor system, having a plurality of CPUs. In FIG. 16, numeral 1 is the information processing apparatus; numeral 2 is a system board; numeral 3 is a CPU bus; numeral 4 is a main memory; numerals 5a to 5d are physical CPUs, assigned with CPU number 0 to 3, transferable of data to and receivable of data from, respectively, the CPU bus 3; numeral 6 is a bus bridge located between the CPU bus 3 and a local bus 7 connecting with peripheral equipment controllers and the like; numerals 8a to 8d are peripheral equipment controllers for controlling equipments of a CRT 9, a keyboard 10, a floppy disk unit 11, a magnetic disk unit 12, respectively, and for transmitting and receiving data to and from the main memory 4; numeral 13 is a ROM for storing an initialization program for setting-up the system when the power is turned on, numeral 14 is a nonvolatile RAM for storing system configuration information indicating such as mounting circumstances of physical CPUs 5a to 5d and configuration information of peripheral equipments.
Numeral 22 is a power-on-reset generator for producing power-on-reset signals for initializing hardware on the system board 2 where the power is turned on; numeral 23 is a power-on-reset signal line for feeding the power-on-reset signals from the power-on-reset generator 22 to the system board 2; numerals 24a to 24d are logical CPU number designation lines, fixedly corresponding to the physical CPUs 5a to 5d, for designating logical CPU numbers of the physical CPUs 5a to 5d.
Now, referring to a flow chart shown in FIG. 17, an initialization operation of the system according to the configuration above will be described. It is presumed that the physical CPU 5a is required to be mounted for operation as a master CPU and that, though all the physical CPUs 5b to 5d are not required to be mounted, they operate as slave CPUs when mounted.
Upon turning the power on of the information processing apparatus 1 (step H1), the power-on-reset generator 22 produces the power-on-reset signal on the power-on-reset signal line 23, and resets the physical CPUs 5a to 5d and the hardware, capable of being reset, provided on the system board 2, then to initialize them (step H2). When the power-on-reset signal indicates as disable, all the mounted physical CPUs 5a to 5d start to implement an initialization program from a specific address in the ROM 13 for storing initialization program. The starting addresses are the same among all the physical CPUs 5a to 5d, and the single initialization program is processed (step H3). The physical CPUs 5a to 5d implement the program in the ROM 13 for storing initialization program and initialize respective required minimum internal hardware. At that time, all the physical CPUs 5a to 5d operates in parallel (step H4).
It is presumed, hereinafter, that the physical CPU 5a assigned to the logical CPU number 0 operates as a master CPU (hereinafter, the physical CPU 5a may be called as a master CPU) and that the other mounted physical CPUs 5b to 5d respectively assigned to the logical CPU numbers 1 to 3 operate as slave CPUs (similarly, hereinafter, the physical CPUs 5b to 5d may be called as slave CPUs). Each physical CPU 5a to 5d, by reading the value at the corresponding logical CPU number designation line 24a to 24d, recognizes the own logical CPU number and judges whether the CPU is the master or slave by itself.
The master CPU 5a implements the program in the ROM 13 for storing initialization program, thereby initializing the entire hardware on the system board 2 except the internal hardware of the master CPU 5a and the slave CPUs (step H5). The master CPU 5a prepares on the main memory 4 a new reset routine existing in the ROM 13 for storing initialization program (step H6). During the process of the master CPU 5a at steps H5, H6, the slave CPUs 5b to 5d stop the processing, and wait for processor reset given from the master CPU 5a (step H7).
The master CPU 5a implements the reset routine in the ROM 13 for storing initialization program, provides the processor reset to all the mounted slave CPU 5b to 5d based on the CPU configuration information stored in the nonvolatile RAM 14 for storing system configuration information (step H8), and waits for report of the completion of initialization for all the mounted slave CPUs (step H9).
During this period, the slave CPUs 5b to 5d, which had stopped the processing, restart upon the processor reset provided from the master CPU 5a, start implementing the new initialization program prepared at step H6 on the main memory 4 (step H10), and initialize the internal hardware of each slave CPU by parallel implementing the initialization program (step H11). The slave CPUs 5b to 5d which have completed the initialization of the internal hardware individually report the completion of initialization to the master CPU 5a (step H12) and then stop the processing again (step H13).
The master CPU 5a, upon receiving the completion report of initialization from those slave CPUs 5b to 5d, starts loading of an initial program from either the floppy disk unit 11 or the magnetic disk unit 12. By this operation, the operating system is set up, and the system of the information processing apparatus 1 starts its operation (step H14).
It is to be noted that the CPU configuration information stored in the nonvolatile RAM 14 for storing the system configuration information is given where a program for altering configuration information registration from either the floppy disk unit 11 or the magnetic disk unit 12 is started and where an operator controls the keyboard in accordance with instructions being displayed on the CRT 9.
As described above, since the conventional symmetric multiprocessor system having a connection by the common bus is thus constituted, the system's constitution is not that each CPU individually implements the initialization process or that the system operation is possible by degenerating defective CPUs, so that the defective CPUs occupy the common bus thereby preventing the system in assistance with other normal CPUs from being set up properly. As the case where the system cannot be set up, It is exemplified, in case that the initialization processing of the master CPU is faulty and, further, in case that the initialization processing of the slave CPU is faulty, the slave CPUs at which a fault occurs may occupy the common bus, thereby stopping the setting-up processing of the system.
In such a situation, even the master CPU monitoring the slave CPUs cannot continue the processing because the system cannot use the common bus, and therefore, it is difficult to set aside the malfunctioning CPUs, as well as the system cannot perform degenerate operation in which the defective CPUs are automatically cut out. Consequently, if a malfunction of the CPU occurs, the system is required to be restarted after any defective CPU is found and physically removed. Therefore, there are problems that, at the occurrence of the fault, urgent manual work is inevitable, that the system becomes useless since it would take so much time to repair the system, and that the system cannot perform an automatic operation by automatic power-on.
In addition, although a CPU having a specific CPU number must exist in order to maintain compatibility with existing software, a normal CPU must be mounted onto a predetermined position because the CPU number of each CPU is fixed at its position to be mounted. Therefore, a problem raises in which it would take so much time to recover the system by works of removing defective CPUs and rearranging normal CPUs.
Since the nonvolatile RAM 14 for storing system configuration information which stores the configuration information of the CPUs is connected to the common bus accessible only from the CPUs, if malfunction of the CPU occurs to force the system to be unable to set up, it is required that first the defective CPUs are found and removed and then the configuration information has to be altered where the hardware is constituted of only normal CPUs. Moreover, since a special program for altering configuration information registration must be executed by normal CPUs to alter the configuration information, the system cannot be handled by remote control, and has to be subject to a poor maintenance. A configuration of the system tends to become a large scale to add functions of automatic degeneration or remote control, because the system has used general-purpose microprocessors and general-purpose chips for peripheral control.
On the other hand, non-stop type computers and general-purpose computers are conventionally equipped with a constitution enabling each CPU to individually implement initialization processing or with a constitution degenerating defective CPUs to start the operation of the system. However, each CPU has a large scale, and the system is equipped with a large-scale exclusive service processor for processing of setting-up or degeneration, so that such computers cost so much.